Gururaj Saileshwar

Research Areas - Computer Architecture and Security.
Assistant Professor in Computer Science, University of Toronto

Email: gururaj@cs.toronto.edu

I am looking for motivated and ambitious PhD students to join my group at the University of Toronto. If you find security for hardware and systems exciting, please reach out to me and apply to the UofT Computer Science program.

My research focuses on improving the security for computing hardware and systems. My research interests include cache side-channels, transient execution attacks, Rowhammer attacks, DRAM integrity, memory safety and fuzzing. Some of my research contributions include:

  • Cache Side-Channels: Enabled the fastest known cache timing attacks [1], randomized cache defenses [2] that end an arms race, and one of the first academic hardware defenses against Spectre [3].
  • DRAM Security: Enabled practical mitigations for DRAM Rowhammer attacks [4, 5] and designed secure memories [6, 7] for protection against physical attacks.
  • Software Reliability: Enabled hardware support for low-cost memory safety [8] and fuzzing [9] to make software resilient to bugs causing a majority of current vulnerabilities.

My work has been awarded a HPCA Best Paper Award, IEEE HOST Best PhD Dissertation Award, ACM SIGARCH / IEEE TCCA Outstanding Dissertation Award (Honorable Mention), ACM SIGMICRO Dissertation Award (Honorable Mention), and a IEEE MICRO Top Picks (Honorable Mention). My PhD was partly supported by a GT Cybersecurity Fellowship and a GT Bourne Fellowship.

I received my PhD at Georgia Tech, Atlanta, USA, where I was advised by Prof. Moinuddin Qureshi. I received my B.Tech and M.Tech at Indian Institute of Technology - Bombay, India. Prior to joining UofT, I was with NVIDIA Research.

teaching

news (full list)

Jun, 2024 Our work, PrIDE, the first secure and low cost in-DRAM mitigation against Rowhammer attacks is presented at ISCA'24.
Aug, 2023 Our CAL-2023 paper Mirage of breaking MIRAGE highlights modeling pitfalls in recent “attacks”, and shows MIRAGE is still unbroken!
Aug, 2023 Serving as a Workshop & Tutorial Chair at MICRO 2023!
Jun, 2023 Awarded the ACM SIGARCH/IEEE CS TCCA Outstanding Dissertation Award (Honorable Mention) at ISCA'23!
Feb, 2023 Our paper Scalable and Secure Row-Swap at HPCA-2023 received the Best Paper Award!
Sep, 2022 Serving as Co-Chair of the Artifact Evaluation Committee at ASPLOS 2023.
Aug, 2022 SQUIP attack (CVE-2021-46778), discovered with collaborators at TU Graz, is public. (techradar, toms hardware, hacker news, ...)
Jun, 2022 Awarded the Best PhD Dissertation Award at IEEE HOST 2022.
Mar, 2022 Invited to serve on the Program Committee (PC) for RAID 2022.
Nov, 2021 Our paper Randomized Row Swap, a principled Rowhammer mitigation accepted at ASPLOS 2022!
Oct, 2021 Invited to serve on the External Review Committee (ERC) for ISCA 2022.
May, 2021 Our paper on Mentoring in Computer Architecture is presented in WCAE at ISCA 2021.
May, 2021 Finalist in the Qualcomm Innovation Fellowship 2021!
Mar, 2021 Invited to serve on the Program Committee (PC) for IEEE S&P (Oakland) 2022.
Mar, 2021 Hardware Support for Fuzzing accepted at CCS 2021!
Mar, 2021 Recognized as Distinguished Reviewer in the Shadow PC of IEEE S&P (Oakland) 2021.
Feb, 2021 MIRAGE, a principled defense vs cache attacks accepted at USENIX Security 2021 [Github].
Jan, 2021 Streamline, the fastest cache covert-channel attack accepted at ASPLOS 2021 [Github].
Jan, 2021 Awarded Georgia Tech IISP Cybersecurity Fellowship!
Nov, 2020 Invited to present MIRAGE at IBM Research's Future of Comp-Arch Workshop 2020.
Apr, 2020 Selected to participate in the 8th Heidelberg Laureate Forum 2020.
Sep, 2019 Invited to present CleanupSpec at IBM Research's Future of Comp-Arch Workshop 2019.
Aug, 2019 CleanupSpec, our work on safe speculation is accepted at MICRO 2019 [Github].
May, 2019 Finalist in Qualcomm Innovation Fellowship 2019!
Jan, 2019 Our paper SYNERGY is awarded an Honorable Mention at IEEE MICRO's Top Picks 2019!
Dec, 2018 Finalist in Microsoft Research PhD Fellowship 2019!
Aug, 2018 Morphable Counters, our work on in-DRAM Merkle Trees is accepted at MICRO 2018 [Github].
Nov, 2017 SYNERGY, our work on co-designing DRAM integrity and reliability accepted at HPCA 2018!

recent publications (full list)

  1. HPCA
    QPRAC: Towards Secure and Practical PRAC-based Rowhammer Mitigation using Priority Queues
    Jeonghyun Woo, Shaopeng (Chris) Lin, Prashant J Nair, Aamer Jaleel, and Gururaj Saileshwar
    In 31st IEEE International Symposium on High Performance Computer Architecture (HPCA) 2025
  2. ISCA
    PrIDE: Achieving Secure Rowhammer Mitigation with Low-Cost In-DRAM Trackers
    Aamer Jaleel, Gururaj Saileshwar, Steven Keckler, and Moinuddin Qureshi
    In 51st International Symposium on Computer Architecture (ISCA) 2024
    PDF Code
  3. DSN
    PT-Guard: Integrity-Protected Page Tables to Defend Against Breakthrough Rowhammer Attacks
    Anish Saxena, Gururaj Saileshwar, Jonas Juffinger, Andreas Kogler, Daniel Gruss, and Moinuddin Qureshi
    In 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN) 2023
    HTML PDF Slides
  4. S&P
    Practical Timing Side-Channel Attacks on Memory Compression
    Martin Schwarzl, Pietro Borrello, Gururaj Saileshwar, Hanna Müller, Michael Schwarz, and Daniel Gruss
    In 44th IEEE Symposium on Security and Privacy (S&P) 2023
    HTML PDF Code
  5. S&P
    SQUIP: Exploiting the Scheduler Queue Contention Side Channel
    Stefan Gast, Jonas Juffinger, Martin Schwarzl, Gururaj Saileshwar, Andreas Kogler, Simone Franza, Markus Kostl, and Daniel Gruss
    In 44th IEEE Symposium on Security and Privacy (S&P) 2023
    HTML PDF Slides
  6. HPCA
    Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems
    Jeonghyun Woo, Gururaj Saileshwar, and Prashant J Nair
    In 29th IEEE International Symposium on High Performance Computer Architecture (HPCA) 2023
    HPCA’23 Best Paper Award
    HTML PDF Slides Code
  7. MICRO
    AQUA: Scalable Rowhammer Mitigation by Quarantining Aggressor Rows at Runtime
    Anish Saxena, Gururaj Saileshwar, Prashant Nair, and Moinuddin Qureshi
    In 55th IEEE/ACM International Symposium on Microarchitecture (MICRO) 2022
    HTML PDF Slides Code
  8. ISCA
    Hydra: Enabling Low-Overhead Mitigation of Row-Hammer at Ultra-Low Thresholds via Hybrid Tracking
    Moinuddin Qureshi, Aditya Rohan, Gururaj Saileshwar, and Prashant Nair
    In 49th International Symposium on Computer Architecture (ISCA) 2022
    HTML PDF Slides
  9. ASPLOS
    Randomized Row Swap: Mitigating Rowhammer Attacks by Breaking Spatial Correlation Between Aggressors and Victims
    Gururaj Saileshwar, Bolin Wang, Moinuddin Qureshi, and Prashant Nair
    In 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2022
    HTML PDF Slides Code
  10. SEC
    MIRAGE: Mitigating Conflict-Based Cache Attacks with a Practical Fully-Associative Design
    Gururaj Saileshwar, and Moinuddin Qureshi
    In 30th USENIX Security Symposium (USENIX Security) 2021
    HTML PDF Slides Video Code SIGARCH Blog