Gururaj Saileshwar

Research Areas - Computer Architecture and Security.
Memory Systems Lab, Georgia Tech

I am a final-year PhD Student (expected graduation: Spring’22) in ECE at Georgia Tech, USA, advised by Prof. Moinuddin Qureshi. My research is at the intersection of Computer Architecture & Systems Security.

My research designs low cost and principled security solutions for hardware. I am interested in a variety of topics at the intersection of computer architecture and security, including cache side-channel resilience, transient execution attacks and defenses in processors, rowhammer attacks and memory integrity, memory safety, and others.

Recently, I spent Summer’21 with Prof. Daniel Gruss’s group at TU Graz, Austria, working on attacking memory compression and reverse-engineering new processor micro-architectures.

During my PhD, I have been fortunate to intern at several industry labs, including ARM Research (Summer’17) on DRAM integrity solutions, Intel Labs - Security (Summer’18) on low-cost memory safety, Microsoft (Summer’19) on principled defenses against processor-speculation attacks, and IBM Research - Security (Summer’20) on hardware for memory-safety.

I received my B.Tech & M.Tech in Electrical Engineering at Indian Institute of Technology - Bombay, India, with a Minor in Computer Science.

news (full list)

Oct, 2021 Invited to serve on the External Review Committee (ERC) for ISCA-2022!
May, 2021 Our paper on Mentoring in Computer Architecture is presented in WCAE-2021 at ISCA-2021.
May, 2021 Finalist in the Qualcomm Innovation Fellowship - 2021.
Mar, 2021 Invited to serve on the Program Committee (PC) for IEEE Security & Privacy (Oakland) 2022!
Mar, 2021 Hardware Support for Fuzzing accepted at CCS-2021!
Mar, 2021 Recognized as Distinguished Reviewer in Shadow PC of IEEE Security & Privacy (Oakland) 2021!
Feb, 2021 MIRAGE, a principled defense vs cache attacks accepted at USENIX Security 2021 [Github].
Jan, 2021 Streamline, the fastest cache covert-channel attack accepted at ASPLOS-2021 [Github].
Jan, 2021 Awarded Georgia Tech IISP Cybersecurity Fellowship!
Nov, 2020 Invited to present MIRAGE at IBM Research's Future of Comp-Arch Workshop 2020.
Apr, 2020 Selected to participate in the 8th Heidelberg Laureate Forum 2020.
Sep, 2019 Invited to present CleanupSpec at IBM Research's Future of Comp-Arch Workshop 2019.
Aug, 2019 CleanupSpec, our work on safe speculation is accepted at MICRO-2019 [Github].
May, 2019 Finalist in Qualcomm Innovation Fellowship 2019.
Jan, 2019 Our paper SYNERGY is awarded an Honorable Mention at IEEE MICRO's Top Picks 2019!
Dec, 2018 Finalist in Microsoft Research PhD Fellowship 2019.
Aug, 2018 Morphable Counters, our work on in-DRAM Merkle Trees is accepted at MICRO-2018 [Github].
Nov, 2017 SYNERGY, our work on co-designing DRAM integrity and reliability accepted at HPCA-2018!

selected publications (full list)

  1. SEC
    MIRAGE: Mitigating Conflict-Based Cache Attacks with a Practical Fully-Associative Design
    Gururaj Saileshwar, and Moinuddin Qureshi
    In 30th USENIX Security Symposium (USENIX Security) 2021
    Streamline: A Fast, Flushless Cache Covert-channel Attack by Enabling Asynchronous Collusion
    Gururaj Saileshwar, Christopher W Fletcher, and Moinuddin Qureshi
    In 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2021
  3. HPCA
    Synergy: Rethinking Secure-memory Design for Error-Correcting Memories
    Gururaj Saileshwar, Prashant J Nair, Prakash Ramrakhyani, Wendy Elsasser, and Moinuddin K Qureshi
    In 24th IEEE International Symposium on High Performance Computer Architecture (HPCA) 2018
    Honorable Mention at IEEE MICRO’s Top Picks 2019