Gururaj Saileshwar

Research Areas - Computer Architecture and Systems Security.
Memory Systems Lab, Georgia Tech

Email: gururaj.s@gatech.edu Office: KACB 1210, Georgia Tech

I am a PhD candidate (expected graduation: May’22) in ECE at Georgia Tech, USA, advised by Prof. Moinuddin Qureshi. My research interests in computer architecture and security include cache side-channels, transient execution attacks, Rowhammer attacks, DRAM integrity, memory safety and fuzzing.

I AM ON THE ACADEMIC JOB MARKET!
[CV] [Research Statement] [Teaching Statement] [Diversity Statement]

My research envisions a future where hardware is secure and free from vulnerabilities, and where trustworthy hardware enables low-cost pervasive security for software systems.

My research has enabled principled security for future hardware and systems at several layers:

  • Cache memories: Enabled the fastest known cache timing attacks [1], randomized cache defenses [2] ending an arms race, and one of the first academic hardware defenses against Spectre [3].
  • DRAM memories: Enabled DRAM integrity solutions [4, 5] that protect against physical attacks, and principled Rowhammer mitigations for current and emerging attacks like Half-Double and Blacksmith.
  • Software reliability: Enabled hardware support for low-cost memory safety [6] and fuzzing [7] that makes software resilient to bugs causing a large majority of current vulnerabilities.

For my work, I have been awarded an IEEE MICRO Top Picks Honorable Mention, the Georgia Tech (IISP) Cybersecurity Fellowship, and the Georgia Tech (ECE) Bourne Fellowship.

I received my B.Tech & M.Tech in Electrical Engineering at Indian Institute of Technology - Bombay, India.

news (full list)

Nov, 2021 Our paper Randomized Row Swap, a principled Rowhammer mitigation accepted at ASPLOS-2022!
Oct, 2021 Invited to serve on the External Review Committee (ERC) for ISCA-2022.
May, 2021 Our paper on Mentoring in Computer Architecture is presented in WCAE-2021 at ISCA-2021.
May, 2021 Finalist in the Qualcomm Innovation Fellowship 2021!
Mar, 2021 Invited to serve on the Program Committee (PC) for IEEE S&P (Oakland) 2022.
Mar, 2021 Hardware Support for Fuzzing accepted at CCS-2021!
Mar, 2021 Recognized as Distinguished Reviewer in the Shadow PC of IEEE S&P (Oakland) 2021.
Feb, 2021 MIRAGE, a principled defense vs cache attacks accepted at USENIX Security 2021 [Github].
Jan, 2021 Streamline, the fastest cache covert-channel attack accepted at ASPLOS-2021 [Github].
Jan, 2021 Awarded Georgia Tech IISP Cybersecurity Fellowship!
Nov, 2020 Invited to present MIRAGE at IBM Research's Future of Comp-Arch Workshop 2020.
Apr, 2020 Selected to participate in the 8th Heidelberg Laureate Forum 2020.
Sep, 2019 Invited to present CleanupSpec at IBM Research's Future of Comp-Arch Workshop 2019.
Aug, 2019 CleanupSpec, our work on safe speculation is accepted at MICRO-2019 [Github].
May, 2019 Finalist in Qualcomm Innovation Fellowship 2019!
Jan, 2019 Our paper SYNERGY is awarded an Honorable Mention at IEEE MICRO's Top Picks 2019!
Dec, 2018 Finalist in Microsoft Research PhD Fellowship 2019!
Aug, 2018 Morphable Counters, our work on in-DRAM Merkle Trees is accepted at MICRO-2018 [Github].
Nov, 2017 SYNERGY, our work on co-designing DRAM integrity and reliability accepted at HPCA-2018!

selected publications (full list)

  1. ASPLOS
    Randomized Row Swap: Mitigating Rowhammer Attacks by Breaking Spatial Correlation Between Aggressors and Victims
    Gururaj Saileshwar, Bolin Wang, Moinuddin Qureshi, and Prashant Nair
    In 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) (To Appear) 2022
  2. CCS
    Hardware Support to Improve Fuzzing Performance and Precision
    Ren Ding, Yonghae Kim, Fan Sang, Wen Xu, Gururaj Saileshwar, and Taesoo Kim
    In 28th ACM Conference on Computer and Communications Security (CCS) 2021
    HTML PDF Slides Code
  3. SEC
    MIRAGE: Mitigating Conflict-Based Cache Attacks with a Practical Fully-Associative Design
    Gururaj Saileshwar, and Moinuddin Qureshi
    In 30th USENIX Security Symposium (USENIX Security) 2021
    HTML PDF Slides Video Code SIGARCH Blog
  4. ASPLOS
    Streamline: A Fast, Flushless Cache Covert-channel Attack by Enabling Asynchronous Collusion
    Gururaj Saileshwar, Christopher W Fletcher, and Moinuddin Qureshi
    In 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2021
    HTML PDF Slides Video Code GT SCS News
  5. MICRO
    Cleanupspec: An "Undo" Approach to Safe Speculation
    Gururaj Saileshwar, and Moinuddin K Qureshi
    In 52nd ACM/IEEE International Symposium on Microarchitecture (MICRO) 2019
    HTML PDF Slides Video Code
  6. MICRO
    Morphable Counters: Enabling Compact Integrity Trees for Low-Overhead Secure Memories
    Gururaj Saileshwar, Prashant J Nair, Prakash Ramrakhyani, Wendy Elsasser, Jose A Joao, and Moinuddin K Qureshi
    In 51st ACM/IEEE International Symposium on Microarchitecture (MICRO) 2018
    HTML PDF Slides Video Code
  7. HPCA
    Synergy: Rethinking Secure-memory Design for Error-Correcting Memories
    Gururaj Saileshwar, Prashant J Nair, Prakash Ramrakhyani, Wendy Elsasser, and Moinuddin K Qureshi
    In 24th IEEE International Symposium on High Performance Computer Architecture (HPCA) 2018
    Honorable Mention at IEEE MICRO’s Top Picks 2019
    HTML PDF Slides Video Code