I am a PhD candidate in ECE at Georgia Tech, USA, advised by Prof. Moinuddin Qureshi. My research interests in computer architecture and security include cache side-channels, transient execution attacks, Rowhammer attacks, DRAM integrity, memory safety and fuzzing.
My past research has improved the security for computing hardware and systems in several ways:
- Cache Side-Channels: Enabled the fastest known cache timing attacks , randomized cache defenses  that end an arms race, and one of the first academic hardware defenses against Spectre .
- DRAM Security: Enabled practical mitigations for DRAM Rowhammer attacks [4, 5] and designed secure memories [6, 7] for protection against physical attacks.
- Software Reliability: Enabled hardware support for low-cost memory safety  and fuzzing  to make software resilient to bugs causing a majority of current vulnerabilities.
My work has been awarded an IEEE MICRO Top Picks Honorable Mention, and been supported in part by GT IISP Cybersecurity Fellowship, and GT ECE Bourne Fellowship.
|Mar, 2022||Invited to serve on the Program Committee (PC) for RAID-2022.|
|Nov, 2021||Our paper Randomized Row Swap, a principled Rowhammer mitigation accepted at ASPLOS-2022!|
|Oct, 2021||Invited to serve on the External Review Committee (ERC) for ISCA-2022.|
|May, 2021||Our paper on Mentoring in Computer Architecture is presented in WCAE-2021 at ISCA-2021.|
|May, 2021||Finalist in the Qualcomm Innovation Fellowship 2021!|
|Mar, 2021||Invited to serve on the Program Committee (PC) for IEEE S&P (Oakland) 2022.|
|Mar, 2021||Hardware Support for Fuzzing accepted at CCS-2021!|
|Mar, 2021||Recognized as Distinguished Reviewer in the Shadow PC of IEEE S&P (Oakland) 2021.|
|Feb, 2021||MIRAGE, a principled defense vs cache attacks accepted at USENIX Security 2021 [Github].|
|Jan, 2021||Streamline, the fastest cache covert-channel attack accepted at ASPLOS-2021 [Github].|
|Jan, 2021||Awarded Georgia Tech IISP Cybersecurity Fellowship!|
|Nov, 2020||Invited to present MIRAGE at IBM Research's Future of Comp-Arch Workshop 2020.|
|Apr, 2020||Selected to participate in the 8th Heidelberg Laureate Forum 2020.|
|Sep, 2019||Invited to present CleanupSpec at IBM Research's Future of Comp-Arch Workshop 2019.|
|Aug, 2019||CleanupSpec, our work on safe speculation is accepted at MICRO-2019 [Github].|
|May, 2019||Finalist in Qualcomm Innovation Fellowship 2019!|
|Jan, 2019||Our paper SYNERGY is awarded an Honorable Mention at IEEE MICRO's Top Picks 2019!|
|Dec, 2018||Finalist in Microsoft Research PhD Fellowship 2019!|
|Aug, 2018||Morphable Counters, our work on in-DRAM Merkle Trees is accepted at MICRO-2018 [Github].|
|Nov, 2017||SYNERGY, our work on co-designing DRAM integrity and reliability accepted at HPCA-2018!|
selected publications (full list)
- ISCAHydra: Enabling Low-Overhead Mitigation of Row-Hammer at Ultra-Low Thresholds via Hybrid TrackingIn 49th International Symposium on Computer Architecture (ISCA) 2022
- ASPLOSRandomized Row Swap: Mitigating Rowhammer Attacks by Breaking Spatial Correlation Between Aggressors and VictimsIn 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2022
- CCSHardware Support to Improve Fuzzing Performance and PrecisionIn 28th ACM Conference on Computer and Communications Security (CCS) 2021
- SECMIRAGE: Mitigating Conflict-Based Cache Attacks with a Practical Fully-Associative DesignIn 30th USENIX Security Symposium (USENIX Security) 2021
- ASPLOSStreamline: A Fast, Flushless Cache Covert-channel Attack by Enabling Asynchronous CollusionIn 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2021
- MICROCleanupspec: An "Undo" Approach to Safe SpeculationIn 52nd ACM/IEEE International Symposium on Microarchitecture (MICRO) 2019
- MICROMorphable Counters: Enabling Compact Integrity Trees for Low-Overhead Secure MemoriesIn 51st ACM/IEEE International Symposium on Microarchitecture (MICRO) 2018
- HPCASynergy: Rethinking Secure-memory Design for Error-Correcting MemoriesIn 24th IEEE International Symposium on High Performance Computer Architecture (HPCA) 2018Honorable Mention at IEEE MICRO’s Top Picks 2019