Gururaj Saileshwar

Research Areas - Computer Architecture and Systems Security.
Assistant Professor in Computer Science, University of Toronto (starting Fall 2023)
Post-Doctoral Researcher, NVIDIA Research (2022 - now)

Email: gururaj@cs.toronto.edu

I am looking for motivated PhD students to join my group at the University of Toronto. If you are interested in working with me and are excited about security for hardware and systems, please reach out to me and apply to the UofT CS graduate program.

My research focuses on improving the security for computing hardware and systems. My research interests include cache side-channels, transient execution attacks, Rowhammer attacks, DRAM integrity, memory safety and fuzzing. Some of my research contributions include:

  • Cache Side-Channels: Enabled the fastest known cache timing attacks [1], randomized cache defenses [2] that end an arms race, and one of the first academic hardware defenses against Spectre [3].
  • DRAM Security: Enabled practical mitigations for DRAM Rowhammer attacks [4, 5] and designed secure memories [6, 7] for protection against physical attacks.
  • Software Reliability: Enabled hardware support for low-cost memory safety [8] and fuzzing [9] to make software resilient to bugs causing a majority of current vulnerabilities.

My work has been awarded an IEEE HOST Best PhD Dissertation Award, an IEEE MICRO Top Picks Honorable Mention, and been supported in part by a GT IISP Cybersecurity Fellowship and a GT ECE Bourne Fellowship.

I received my PhD in Electrical and Computer Engineering at Georgia Tech, USA, while being advised by Prof. Moinuddin Qureshi, and received my B.Tech & M.Tech in Electrical Engineering from Indian Institute of Technology - Bombay, India.

news (full list)

Sep, 2022 Serving as Co-Chair of the Artifact Evaluation Committee at ASPLOS 2023.
Aug, 2022 SQUIP attack (CVE-2021-46778), discovered with collaborators at TU Graz, is public. (techradar, toms hardware, hacker news, ...)
Jun, 2022 Awarded the Best PhD Dissertation Award at IEEE HOST 2022.
Mar, 2022 Invited to serve on the Program Committee (PC) for RAID 2022.
Nov, 2021 Our paper Randomized Row Swap, a principled Rowhammer mitigation accepted at ASPLOS 2022!
Oct, 2021 Invited to serve on the External Review Committee (ERC) for ISCA 2022.
May, 2021 Our paper on Mentoring in Computer Architecture is presented in WCAE at ISCA 2021.
May, 2021 Finalist in the Qualcomm Innovation Fellowship 2021!
Mar, 2021 Invited to serve on the Program Committee (PC) for IEEE S&P (Oakland) 2022.
Mar, 2021 Hardware Support for Fuzzing accepted at CCS 2021!
Mar, 2021 Recognized as Distinguished Reviewer in the Shadow PC of IEEE S&P (Oakland) 2021.
Feb, 2021 MIRAGE, a principled defense vs cache attacks accepted at USENIX Security 2021 [Github].
Jan, 2021 Streamline, the fastest cache covert-channel attack accepted at ASPLOS 2021 [Github].
Jan, 2021 Awarded Georgia Tech IISP Cybersecurity Fellowship!
Nov, 2020 Invited to present MIRAGE at IBM Research's Future of Comp-Arch Workshop 2020.
Apr, 2020 Selected to participate in the 8th Heidelberg Laureate Forum 2020.
Sep, 2019 Invited to present CleanupSpec at IBM Research's Future of Comp-Arch Workshop 2019.
Aug, 2019 CleanupSpec, our work on safe speculation is accepted at MICRO 2019 [Github].
May, 2019 Finalist in Qualcomm Innovation Fellowship 2019!
Jan, 2019 Our paper SYNERGY is awarded an Honorable Mention at IEEE MICRO's Top Picks 2019!
Dec, 2018 Finalist in Microsoft Research PhD Fellowship 2019!
Aug, 2018 Morphable Counters, our work on in-DRAM Merkle Trees is accepted at MICRO 2018 [Github].
Nov, 2017 SYNERGY, our work on co-designing DRAM integrity and reliability accepted at HPCA 2018!

selected publications (full list)

  1. S&P
    SQUIP: Exploiting the Scheduler Queue Contention Side Channel
    Stefan Gast, Jonas Juffinger, Martin Schwarzl, Gururaj Saileshwar, Andreas Kogler, Simone Franza, Markus Kostl, and Daniel Gruss
    In 44th IEEE Symposium on Security and Privacy (S&P) 2023
    PDF
  2. MICRO
    AQUA: Scalable Rowhammer Mitigation by Quarantining Aggressor Rows at Runtime
    Anish Saxena, Gururaj Saileshwar, Prashant Nair, and Moinuddin Qureshi
    In 55th IEEE/ACM International Symposium on Microarchitecture 2022
  3. ISCA
    Hydra: Enabling Low-Overhead Mitigation of Row-Hammer at Ultra-Low Thresholds via Hybrid Tracking
    Moinuddin Qureshi, Aditya Rohan, Gururaj Saileshwar, and Prashant Nair
    In 49th International Symposium on Computer Architecture (ISCA) 2022
    HTML PDF
  4. ASPLOS
    Randomized Row Swap: Mitigating Rowhammer Attacks by Breaking Spatial Correlation Between Aggressors and Victims
    Gururaj Saileshwar, Bolin Wang, Moinuddin Qureshi, and Prashant Nair
    In 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2022
    HTML PDF Slides Code
  5. CCS
    Hardware Support to Improve Fuzzing Performance and Precision
    Ren Ding, Yonghae Kim, Fan Sang, Wen Xu, Gururaj Saileshwar, and Taesoo Kim
    In 28th ACM Conference on Computer and Communications Security (CCS) 2021
    HTML PDF Slides Code
  6. SEC
    MIRAGE: Mitigating Conflict-Based Cache Attacks with a Practical Fully-Associative Design
    Gururaj Saileshwar, and Moinuddin Qureshi
    In 30th USENIX Security Symposium (USENIX Security) 2021
    HTML PDF Slides Video Code SIGARCH Blog
  7. ASPLOS
    Streamline: A Fast, Flushless Cache Covert-channel Attack by Enabling Asynchronous Collusion
    Gururaj Saileshwar, Christopher W Fletcher, and Moinuddin Qureshi
    In 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2021
    HTML PDF Slides Video Code GT SCS News
  8. MICRO
    Cleanupspec: An "Undo" Approach to Safe Speculation
    Gururaj Saileshwar, and Moinuddin K Qureshi
    In 52nd ACM/IEEE International Symposium on Microarchitecture (MICRO) 2019
    HTML PDF Slides Video Code
  9. MICRO
    Morphable Counters: Enabling Compact Integrity Trees for Low-Overhead Secure Memories
    Gururaj Saileshwar, Prashant J Nair, Prakash Ramrakhyani, Wendy Elsasser, Jose A Joao, and Moinuddin K Qureshi
    In 51st ACM/IEEE International Symposium on Microarchitecture (MICRO) 2018
    HTML PDF Slides Video Code
  10. HPCA
    Synergy: Rethinking Secure-memory Design for Error-Correcting Memories
    Gururaj Saileshwar, Prashant J Nair, Prakash Ramrakhyani, Wendy Elsasser, and Moinuddin K Qureshi
    In 24th IEEE International Symposium on High Performance Computer Architecture (HPCA) 2018
    Honorable Mention at IEEE MICRO’s Top Picks 2019
    HTML PDF Slides Video Code